PSD4135F-C-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD4135F-C-20UI Datasheet PDF : 110 Pages
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PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
PSD835G2
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
G have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode for all port pins is input.
Figures 26 and 28 show the Port Architecture diagrams for Ports A/B/C and E/F/G
respectively. The direction of data flow for Ports A, B, C and F are controlled not only by
the direction register, but also by the output enable product term from the PLD AND array.
If the output enable product term is not active, the Direction Register has sole control of a
given pin’s direction.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 22. Since Port D only contains four pins,
the Direction Register for Port D has only the four least significant bits active.
Table 20. Port Pin Direction Control,
Output Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Table 21. Port Pin Direction Control, Output Enable P.T. Defined
Direction Register Bit Output Enable P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 22. Port Direction Assignment Example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
0
Bit 2
1
Bit 1
1
Bit 0
1
58
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