PSD803F1V-C-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD803F1V-C-70UI Datasheet PDF : 110 Pages
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PSD835G2
PSD8XX Family
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write Timing (3.0 V to 3.6 V Versions)
Symbol
t LVLX
t AVLX
t LXAX
t AVWL
t SLWL
t DVWH
t WHDX
t WLWH
t WHAX1
t WHAX2
t WHPV
t WLMV
t DVMV
t AVPV
Parameter
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
WR Valid to Port Output Valid Using
Micro⇔Cell Register Preset/Clear
Data Valid to Port Output Valid
Using Micro⇔Cell Register Preset/Clear
Address Input Valid to Address
Output Delay
Conditions
(Note 1)
(Note 1)
(Notes 1 and 3)
(Note 3)
(Note 3)
(Notes 3 and 7)
(Note 3)
(Note 3)
(Notes 3 and 6)
(Note 3)
(Notes 3 and 4)
(Notes 3 and 5)
(Note 2)
-90
-12
Min Max Min Max Unit
22
24
7
9
ns
8
10
ns
15
18
ns
15
18
ns
40
45
ns
5
8
ns
40
45
ns
8
10
ns
0
0
ns
33
33 ns
65
70 ns
65
68 ns
30
35 ns
NOTES: 1. Any input used to select an internal PSD835G2 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E and DS signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
7. tWHDX is 11ns when writing to the Output Micro⇔Cell Registers AB and BC.
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