PIC16CR62A-04E/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

PIC16CR62A-04E/SO

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

8.5 Resetting Timer1 using a CCP Trigger

Output

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

CCP2 is implemented on the PIC16C63/R63/65/65A/

R65/66/67 only.

If CCP1 or CCP2 module is configured in Compare

mode to generate a “special event trigger”

(CCPxM3:CCPxM0 = 1011), this signal will reset

Timer1.

Note:

The “special event trigger” from the

CCP1and CCP2 modules will not set inter-

rupt flag bit TMR1IF(PIR1<0>).

Timer1 must be configured for either timer or synchro-

nized counter mode to take advantage of this feature.

If the Timer1 is running in asynchronous counter mode,

this reset operation may not work.

In the event that a write to Timer1 coincides with a spe-

cial event trigger from CCP1 or CCP2, the write will

take precedence.

In this mode of operation, the CCPRxH:CCPRxL regis-

ters pair effectively becomes the period register for the

Timer1 module.

8.6 Resetting of TMR1 Register Pair

(TMR1H:TMR1L)

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The TMR1H and TMR1L registers are not reset to 00h

on a POR or any other reset except by the CCP1 or

CCP2 special event trigger.

The T1CON register is reset to 00h on a Power-on

Reset or a Brown-out Reset, which shuts off the timer

and leaves a 1:1 prescaler. In all other resets, the reg-

ister is unaffected.

8.7 Timer1 Prescaler

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE T0IE

10Bh,18Bh

INTE

RBIE

T0IF INTF RBIF 0000 000x 0000 000u

0Ch

PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch

PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

0Eh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.

2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.

3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.

DS30234D-page 74

© 1997 Microchip Technology Inc.

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