PIC12C5XX
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
GP3/MCLR/VPP
Power-Up
Detect
POR (Power-On Reset)
Pin Change
SLEEP
Wake-up on
pin change
MCLRE
On-Chip
DRT OSC
WDT Time-out
RESET
8-bit Asynch
S
Ripple Counter
(Start-Up Timer)
R
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
Q
Q
CHIP RESET
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
DRT TIME-OUT
INTERNAL RESET
TDRT
© 1999 Microchip Technology Inc.
DS40139E-page 41