PCA9541BS/03 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCA9541BS/03

2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9541

2-to-1 I2C-bus master selector with interrupt logic and reset

SDA_MST0(1)

slave address

command code register

data Control register

After the STOP condition MASTER 1

is disconnected from the downstream

channel, and MASTER 0 is connected to

the downstream channel.

S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 0 0 1 0 0 A P

START condition

R/W

acknowledge

from slave

auto

increment

acknowledge

from slave

SCL_MST0

BUSINIT

BUSON

MYBUS

STOP

condition

acknowledge

from slave

INT1

INT0

if the interrupt is not masked

(BUSLOSTMSK = 0)

if MASTER 1 was not idle at the switching moment

and the interrupt is not masked (BUSINITMSK = 0)

MASTER 1 has control of the bus

MASTER 0 has control of the bus

MASTER 0 must wait for the 'bus free time' value

(between STOP and START) defined in the I2C-bus specification

before sending commands to the downstream devices.

002aab610

(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read

(MASTER 1 controlling the bus).

Fig 16. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization not

requested)

PCA9541_7

Product data sheet

Rev. 07 — 2 July 2009

© NXP B.V. 2009. All rights reserved.

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