MCP3903T-I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
MCP3903T-I/SS Datasheet PDF : 54 Pages
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MCP3903
7.0 INTERNAL REGISTERS
The addresses associated with the internal registers
are listed below. All registers are 24 bits long and can
be addressed separately. A detailed description of the
registers follows.
.
TABLE 7-1:
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
INTERNAL REGISTER SUMMARY
Name
Bits R/W
Description
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
MOD
PHASE
GAIN
STATUS/COM
CONFIG
24 R Channel 0 ADC Data <23:0>, MSB first, left justified
24 R Channel 1 ADC Data <23:0>, MSB first, left justified
24 R Channel 2 ADC Data <23:0>, MSB first, left justified
24 R Channel 3 ADC Data <23:0>, MSB first, left justified
24 R Channel 4 ADC Data <23:0>, MSB first, left justified
24 R Channel 5 ADC Data <23:0>, MSB first, left justified
24 R/W Delta Sigma Modulators Output Value
24 R/W Phase Delay Configuration Register
24 R/W Gain Configuration Register
24 R/W Status/Communication Register
24 R/W Configuration Register
The following table shows how the internal address
counter will loop on specific register groups and types.
TABLE 7-2:
CONTINUOUS READ
OPTIONS, LOOPING ON
INTERNAL ADDRESSES
READ<1:0>
Function Address = “01” = “10” =“11”
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
MOD
PHASE
GAIN
STATUS/
COM
CONFIG
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GROUP
GROUP
GROUP
7.1 Channel Output Registers
TABLE 7-3: ADC OUTPUT REGISTERS
Name
Bits
Address
Cof
CHANNEL 0
24
0x00
R
CHANNEL 1
24
0x01
R
CHANNEL 2
24
0x02
R
CHANNEL 3
24
0x03
R
CHANNEL 4
24
0x04
R
CHANNEL 5
24
0x05
R
The ADC Channel data output registers always contain
the most recent A/D conversion data for each channel.
These registers are read-only. They can be accessed
independently or linked together (with READ<1:0>
bits). These registers are latched when an ADC read
communication occurs. When a data ready event
occurs during a read communication, the most current
ADC data is also latched to avoid data corruption
issues. The three bytes of each channel are updated
synchronously at a DRCLK rate. The three bytes can
be accessed separately if needed, but are refreshed
synchronously. The coding is 23-bit + sign two’s
complement (see Section 5.5).
© 2011 Microchip Technology Inc.
DS25048B-page 37
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