MC68HC811L1MFS3 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MC68HC811L1MFS3 Datasheet PDF : 124 Pages
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Freescale Semiconductor, Inc.
Table 3-2 Instruction Set (Sheet 6 of 7)
Mnemonic Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode Operand Cycles S X H I N Z V C
SBCA (opr) Subtract with
Carry from A
A–M–C⇒A A
A
A
A
A
IMM
DIR
EXT
IND,X
IND,Y 18
82 ii
92 dd
B2 hh ll
A2 ff
A2 ff
2
———— ∆ ∆ ∆ ∆
3
4
4
5
SBCB (opr) Subtract with
Carry from B
B–M–C⇒B B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y 18
C2 ii
D2 dd
F2 hh ll
E2 ff
E2 ff
2
———— ∆ ∆ ∆ ∆
3
4
4
5
SEC
Set Carry
1⇒C
INH
0D
—
2
——————— 1
SEI
Set Interrupt
Mask
1⇒I
INH
0F
—
2
——— 1 ————
SEV
Set Overflow
Flag
1⇒V
INH
0B
—
2
—————— 1 —
STAA (opr)
Store
Accumulator
A
A⇒M
A
DIR
97 dd
A
EXT
B7 hh ll
A
IND,X
A7 ff
A
IND,Y 18
A7 ff
3
———— ∆ ∆ 0 —
4
4
5
STAB (opr)
Store
Accumulator
B
B⇒M
B
DIR
D7 dd
B
EXT
F7 hh ll
B
IND,X
E7 ff
B
IND,Y 18
E7 ff
3
———— ∆ ∆ 0 —
4
4
5
STD (opr)
Store
Accumulator
D
A ⇒ M, B ⇒ M + 1
DIR
EXT
IND,X
IND,Y 18
DD dd
FD hh ll
ED ff
ED ff
4
———— ∆ ∆ 0 —
5
5
6
STOP
Stop Internal
—
Clocks
INH
CF
—
2
————————
STS (opr)
Store Stack
Pointer
SP ⇒ M : M + 1
DIR
EXT
IND,X
IND,Y 18
9F dd
BF hh ll
AF ff
AF ff
4
———— ∆ ∆ 0 —
5
5
6
STX (opr)
Store Index
Register X
IX ⇒ M : M + 1
DIR
EXT
IND,X
IND,Y CD
DF dd
FF hh ll
EF ff
EF ff
4
———— ∆ ∆ 0 —
5
5
6
STY (opr)
Store Index
Register Y
IY ⇒ M : M + 1
DIR
18
EXT 18
IND,X 1A
IND,Y 18
DF dd
FF hh ll
EF ff
EF ff
5
———— ∆ ∆ 0 —
6
6
6
SUBA (opr)
Subtract
A–M⇒A
A
IMM
Memory from
A
DIR
A
A
EXT
80 ii
90 dd
B0 hh ll
2
———— ∆ ∆ ∆ ∆
3
4
A
IND,X
A0 ff
4
A
IND,Y 18
A0 ff
5
SUBB (opr)
Subtract
Memory from
B
B–M⇒B
A
A
A
A
A
IMM
DIR
EXT
IND,X
IND,Y 18
C0 ii
D0 dd
F0 hh ll
E0 ff
E0 ff
2
———— ∆ ∆ ∆ ∆
3
4
4
5
SUBD (opr)
Subtract
Memory from
D
D–M:M+1⇒D
IMM
DIR
EXT
IND,X
IND,Y 18
83 jj kk
93 dd
B3 hh ll
A3 ff
A3 ff
4
———— ∆ ∆ ∆ ∆
5
6
6
7
SWI
Software
See Figure 3–2
INH
Interrupt
3F
—
14 — — — 1 — — — —
TAB
Transfer A to B
A⇒B
INH
16
—
2
———— ∆ ∆ 0 —
TAP
Transfer A to
A ⇒ CCR
CC Register
INH
06
—
2
∆↓∆∆∆∆∆∆
TBA
Transfer B to A
B⇒A
INH
17
—
2
———— ∆ ∆ 0 —
TEST
TEST (Only in Address Bus Counts
INH
Test Modes)
00
—
*
————————
TPA
Transfer CC
CCR ⇒ A
Register to A
INH
07
—
2
————————
TST (opr)
Test for Zero
or Minus
M–0
EXT
IND,X
IND,Y 18
7D hh ll
6D ff
6D ff
6
———— ∆ ∆ 0 0
6
7
TSTA
Test A for Zero
or Minus
A–0
A
INH
4D
—
2
———— ∆ ∆ 0 0
TSTB
Test B for Zero
or Minus
B–0
B
INH
5D
—
2
———— ∆ ∆ 0 0
TECHNICAL DATA
CENTRAL PROCESSING UNIT
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