Low-Voltage, Combination Single-Ended
8-to-1/Differential 4-to-1 Multiplexer
Test Circuits/Timing Diagrams
(continued)
+5V
____________________Chip Topography
A0 A1 COMB GND A2
A3
NLATCH
A3
V+
NO1
CHANNEL
A2 MAX4598 NO8
1MHz
CAPACITANCE
NO4
SELECT
A1
ANALYZER
COM_
NO2
A0
LATCH,
GND EN V-
NO3
-5V
NO1
Figure 6. NO_/COM_ Capacitance
NO8
0.104"
(2.64mm)
NO6
NO7
NO5
+5V
EN V+
+3V
NO2
LATCH
NO1, NO3–NO8
A1
A0
A2 MAX4598
A3
NLATCH
COM
GND
V-
-5V
V- V+
COMA LATCH
EN
NLATCH
0.092"
(2.34mm)
TRANSISTOR COUNT: 287
SUBSTRATE CONNECTED TO V+
LATCH
ADDRESS
50%
tS
tH
VIH
VIL
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS
VIH - VIL
2
Figure 7. Setup Time, Hold Time
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