M95256-WMN6TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M95256-WMN6TP

256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95256, M95128

POWER-UP AND DELIVERY STATE

Power-up State

After Power-up, the device is in the following state:

– Standby Power mode

– deselected (after Power-up, a falling edge is

required on Chip Select (S) before any

instructions can be started).

– not in the Hold Condition

– the Write Enable Latch (WEL) is reset to 0

– Write In Progress (WIP) is reset to 0

The SRWD, BP1 and BP0 bits of the Status Reg-

ister are unchanged from the previous power-

down (they are non-volatile bits).

Initial Delivery State

The device is delivered with the memory array set

at all 1s (FFh). The Status Register Write Disable

(SRWD) and Block Protect (BP1 and BP0) bits are

initialized to 0.

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