M50FLW040ANB5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M50FLW040ANB5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Bus operations

Table 6. FWH bus read field definitions

Clock Clock

Cycle Cycle

Number Count

Field

FWH0- Memory

FWH3 I/O

Description

1

1 START 1101b

I

On the rising edge of CLK with FWH4 Low, the contents

of FWH0-FWH3 indicate the start of a FWH Read cycle.

Indicates which FWH Flash Memory is selected. The

2

1 IDSEL XXXX

I

value on FWH0-FWH3 is compared to the IDSEL

strapping on the FWH Flash Memory pins to select

which FWH Flash Memory is being addressed.

A 28-bit address is transferred, with the most significant

nibble first. For the multi-byte read operation, the least

significant bits (MSIZE of them) are treated as Don't

3-9

7 ADDR XXXX

I

Care, and the read operation is started with each of

these bits reset to 0. Address lines A19-21 and A23-27

are treated as Don’t Care during a normal memory

array access, with A22=1, but are taken into account for

a register access, with A22=0. (See Table 15)

This one clock cycle is driven by the host to determine

the number of Bytes that will be transferred.

10

1 MSIZE XXXX

I M50FLW040 supports: single Byte transfer (0000b), 2-

Byte transfer (0001b), 4-Byte transfer (0010b), 16-Byte

transfer (0100b) and 128-Byte transfer (0111b).

11

1

TAR 1111b

I

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

12

1

TAR

1111b

(float)

O

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

13-14

2 WSYNC 0101b

The FWH Flash Memory drives FWH0-FWH3 to 0101b

O

(short wait-sync) for two clock cycles, indicating that the

data is not yet available. Two wait-states are always

included.

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

15

1 RSYNC 0000b O indicating that data will be available during the next

clock cycle.

16-17 M=2n DATA XXXX

Data transfer is two CLK cycles, starting with the least

O

significant nibble. If multi-Byte read operation is

enabled, repeat cycle-16 and cycle-17 n times, where

n = 2MSIZE.

previous

+1

1

TAR 1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b

to indicate a turnaround cycle.

previous

+1

1

TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs, the host

takes control of FWH0-FWH3.

21/64

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