M45PE20-VMN6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M45PE20-VMN6

2 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface

STMicroelectronics 

M45PE20

Read Data Bytes at Higher Speed

(FAST_READ)

The device is first selected by driving Chip Select

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of Serial Clock (C). Then the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 12..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, therefore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any time during data output. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 12. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out

Sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

Instruction

24 BIT ADDRESS

D

23 22 21

3210

High Impedance

Q

S

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

C

Dummy Byte

D

76543210

DATA OUT 1

DATA OUT 2

Q

76543210765432107

MSB

MSB

MSB

AI04006

Note: Address bits A23 to A18 are Don’t Care.

16/35

Share Link: