M28F420-80N6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M28F420-80N6TR Datasheet PDF : 38 Pages
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M28F410, M28F420
shows the status of the P/E.C. Bit b7 = ’1’ indicates
that programming is completed.
A full status check can be made after each
byte/word or after a sequence of data has been
programmed. The status check is made on bit b3
for any possible VPP error and on bit b4 for any
possible programming error.
Erase. The memory can be erased by blocks. The
Program Supply voltage VPP must be applied be-
fore the Erase instruction is given, and if the Erase
is of the Boot Block RP must also be raised to VHH
to unlock the Boot Block. The Erase sequence is
started by writing an Erase Set-up command (20h)
to the Command Interface, this is followed by an
address in the block to be erased and the Erase
Confirm command (0D0h).
The Program/Erase Controller automatically starts
and performs the block erase, providing the VPP
voltage (and the RP voltage if the erase is of the
Boot Block) is correct. During the erase the memory
status is checked by reading the status register bit
b7 which shows the status of the P/E.C. Bit b7 =
’1’ indicates that erase is completed.
A full status check can be made after the block
erase by checking bit b3 for any possible VPP error,
bits b5 and b6 for any command sequence errors
(erase suspended) and bit b5 alone for an erase
error.
Reset. Note that after any program or erase in-
struction has completed with an error indication or
after any VPP transitions down to VPPL the Com-
mand Interface must be reset by a Clear Status
Register Instruction before data can be accessed.
Automatic Power Saving
The M28F410 and M28F420 memories place
themselves in a lower power state when not being
accessed. Following a Read operation, after a
delay equal to the memory access time, the Supply
Current is reduced from a typical read current of
25mA (CMOS inputs, word-wide organization) to
less than 2mA.
Power Down
The memories provide a power down control input
RP. When this signal is taken to below VSS + 0.2V
all internal circuits are switched off and the supply
current drops to typically 0.2μA and the program
current to typically 0.1μA. If RP is taken low during
a memory read operation then the memory is de-
selected and the outputs become high impedance.
If RP is taken low during a program or erase
sequence then it is aborted and the memory con-
tent is no longer valid.
Recovery from deep power down requires 300ns
to a memory read operation, or 210ns to a com-
mand write. On return from power down the status
register is cleared to 00h.
Power Up
The Supply voltage VCC and the Program Supply
voltage VPP can be applied in any order. The mem-
ory Command Interface is reset on power up to
Read Memory Array, but a negative transition of
Chip Enable E or a change of the addresses is
required to ensure valid data outputs. Care must
be taken to avoid writes to the memory when VCC
is above VLKO and VPP powers up first. Writes can
be inhibited by driving either E or W to VIH. The
memory is disabled until RP is up to VIH.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the VCC and VPP rails decoupled with a 0.1μF
capacitor close to the VCC and VSS pins. The PCB
trace widths should be sufficient to carry the VPP
program and erase currents required.
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