M28F201-120N6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M28F201-120N6TR Datasheet PDF : 21 Pages
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M28F201
Figure 12. Erasing Flowchart
VPP = 12V
PROGRAM ALL
BYTES TO 00h
n=0, Addr=00000h
ERASE SET-UP
Wait 10ms
NO
YES
++n
=
1000
ERASE VERIFY
Latch Addr.
Wait 6µs
VPP < 6.5V
FAIL
READ DATA OUTPUT
NO Data
OK
YES
Addr++
Last NO
Addr
YES
READ COMMAND
VPP < 6.5V, PASS
AI00649
Figure 13. Programming Flowchart
VPP = 12V
n =0
PROGRAM SET-UP
Latch Addr, Data
Wait 10µs
NO
YES ++n
= 25
PROGRAM VERIFY
Wait 6µs
VPP < 6.5V
FAIL
READ DATA OUTPUT
NO Data
OK
YES
Addr++
Last NO
Addr
YES
READ COMMAND
VPP < 6.5V, PASS
AI00677
PRESTO F ERASE ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programs all bytes to 00h in order to
ensure uniform erasure. The programming follows
the PRESTO F Programming Algorithm. Erase is
set-up by writing 20h to the command register, the
erasure is started by repeating this write cycle.
Erase Verify is set-up by writing A0h to the com-
mand register together with the address of the byte
to be verified. The subsequentread cycle reads the
data which is compared to FFh. Erase Verify begins
at address 0000h and continues to the last address
or until the comparison of the data to FFh fails. If
this occurs, the address of the last byte checked is
stored and a new Erase operation performed.
Erase Verify then continues from the address of the
stored location.
PRESTO F PROGRAM ALGORITHM
The PRESTO F Programming Algorithm applies a
series of 10µs programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-up by writing 40h to the command register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected. During Program and Program Verify op-
erations a MARGIN MODE circuit is activated to
guaranteethat the cell is programmed with a safety
margin.
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