M25P40SVMN6PXA View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

MFG CO.

M25P40SVMN6PXA

4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

M25P40

Instructions

Table 7. Protection modes

W SRWD

signal bit

Mode

Write Protection of the

Status Register

Memory content

Protected area(1) Unprotected area(1)

1

0

Status Register is

Writable (if the WREN

0

0 Software instruction has set the

Protected against Ready to accept

Protected WEL bit)

Page Program,

Page Program and

Sector Erase and Sector Erase

1

1

(SPM) The values in the SRWD, Bulk Erase

instructions

BP2, BP1 and BP0 bits

can be changed

Status Register is

Hardware Hardware write protected Protected against Ready to accept

Page Program,

Page Program and

0

1 Protected The values in the SRWD, Sector Erase and Sector Erase

(HPM) BP2, BP1 and BP0 bits Bulk Erase

instructions

cannot be changed

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in

Table 2.

The protection features of the device are summarized in Table 7.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

„ If Write Protect (W) is driven High, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

„ If Write Protect (W) is driven Low, it is not possible to write to the Status Register even

if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Register, are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

„ by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

„ or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

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