M25P40SVMN6TGX View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

MFG CO.

M25P40SVMN6TGX

4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P40

6.2

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

„ Power-up

„ Write Disable (WRDI) instruction completion

„ Write Status Register (WRSR) instruction completion

„ Page Program (PP) instruction completion

„ Sector Erase (SE) instruction completion

„ Bulk Erase (BE) instruction completion

Figure 8. Write Disable (WRDI) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

20/57

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