M25P10-VMN6T View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M25P10-VMN6T

1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface

STMicroelectronics 

M25P10

Figure 17. RES: Release from Deep Power Down Mode Sequence

S

01234567

tRES

C

INSTRUCTION

D

HIGH IMPEDANCE

Q

Deep Power Down Mode Stand-by Power Down Mode

AI03754

mode. At the same time, the RES instruction

provides the Electronic Signature of the device on

the Q output pin. At power down, the Deep Down

Mode is automatically discarded. This causes the

device to always wake up in the Standby Power

Mode state after power-on.

The DP instruction is entered by driving the Chip

select input (S) low, followed by the instruction

byte on Data In input (D). The Chip Select input (S)

must be driven low for the entire duration of the

sequence. The device must be deselected just

after the eighth bit of the instruction byte has been

latched in. If not, the DP instruction is not

executed. As soon as the device is deselected, it

requires tDP to enter the Deep Power Down Mode

where standby current is reduced to ICC2.

The timing sequence is shown in Figure 15.

Release from Deep Power Down Mode and

Read Electronic Signature (RES)

Once the device has entered the Deep Power

Down Mode, all instructions are ignored except the

RES instruction which releases the part from this

mode. At the same time, the RES instruction

provides the Electronic Signature of the device on

the Q output pin. Except during an Erase, Program

cycle or Write Status register, the RES instruction

always provides access to the Electronic

Signature of the device and can be applied even if

the Deep Power Down Mode has not been

entered. Any RES attempt during an Erase,

Program cycle or Write Status register, will be

rejected and will deselect the chip without having

any effects on the ongoing Erase, Program cycle

or Write Status Register.

The device is first selected by putting S low. The

RES instruction byte is followed by a dummy three

bytes address (A23-A0), each bit being latched-in

on Data In input (D) during the rising edge of the

clock (C). Then, the Electronic Signature stored in

the memory is shifted out on the Q output pin,

each bit being shifted out during the falling edge of

the clock (C). It is possible to continuously read the

Electronic Signature value. The RES operation is

terminated by deselecting the chip after the

Electronic Signature has been read at least one

time (see Figure 16). At this step, the device is

immediately put again in the Standby Power Mode

state. It waits for a select condition and is able to

receive, decode and execute all instructions.

Deselecting the device after the 8 bits RES

instruction has been sent but before the LSB of the

Electronic Signature has been read, will insure the

Deep Power Down Mode to be released but will

generate a delay (tRES) before the device is put in

Standby Power Mode state (see Figure 17) and S

must remain high for at least tRES max value (see

Table 13).

POWER ON STATE

At Power-up, the device must not be selected (that

is the S input must follow the voltage supplied on

the VCC pin) until the supply voltage reaches the

minimum VCC value (2.7 V). Once VCC has

reached the minimum operating voltage (2.7 V),

the Chip Select input pin (S) must remain high for

a time higher than tVSL min (See Table 8).

After a Power up, the memory is in the following

state:

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