LTC4160EPDC-PBF View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC4160EPDC-PBF

Switching Power Manager with USB On-The-Go And Overvoltage Protection

Linear Technology 

LTC4160/LTC4160-1

APPLICATIONS INFORMATION

LTC4160/

LTC4160-1

ENOTG

ON-THE-GO

TRANSCEIVER

OVSENS

OVGATE

OVP

(OPTIONAL)

VBUS

CB

<6.5μF

WITHOUT OVP

CA

<6.5μF FOR OTG DEVICES

>96μF FOR STANDARD HOST

D–

D+

STANDARD

USB HOST OR

ON-THE-GO

POWER

MANAGER

STANDARD OR

ON-THE-GO

TRANSCEIVER

B DEVICE

Figure 10. LTC4160/LTC4160-1 as the B Device

A DEVICE 41601 F12

41601 F11

Figure 11. Higher Frequency Ground Current Follow Their

Incident Path. Slices in the Ground Plane Create Large Loop

Areas. The Large Loop Areas Increase the Inductance of the Path

Leading to Higher System Noise.

The IDGATE pin for the external ideal diode controller has

extremely limited drive current. Care must be taken to

minimize leakage to adjacent PC board traces. 100nA of

leakage from this pin will introduce an additional offset to

the ideal diode of approximately 10mV. To minimize leakage,

the trace can be guarded on the PC board by surrounding

it with VOUT connected metal, which should generally be

less than one volt higher than IDGATE.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC4160/LTC4160-1:

1. The Exposed Pad of the package (Pin 21) should connect

directly to a large ground plane to minimize thermal and

electrical impedance.

2. The trace connecting VBUS to its respective decoupling

capacitor should be as short as possible. The GND

side of these capacitors should connect directly to the

ground plane of the part. These capacitors provide the

AC current to the internal power MOSFETs and their

drivers. It is critical to minimize inductance from these

capacitors to the LTC4160/LTC4160-1.

3. Connections between the PowerPath switching regulator

inductor and the output capacitor on VOUT should be kept

as short as possible. Use area fills whenever possible.

The GND side of the output capacitors should connect

directly to the thermal ground plane of the part.

4. The switching power trace connecting SW to its respec-

tive inductor should be minimized to reduce radiated

EMI and parasitic coupling.

41601f

27

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