LTC3403EDD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3403EDD Datasheet PDF : 16 Pages
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LTC3403
PI FU CTIO S
GDR (Pin 1): MOSFET Gate Driver. Drives a small external
P-channel MOSFET.
VIN (Pin 2): Main Supply Pin. Must be closely decoupled
to GND, Pin 3, with a 10µF or greater ceramic capacitor.
GND (Pin 3): Ground Pin.
SW (Pin 4): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
RUN (Pin 5): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1µA supply current. Do not leave RUN floating.
MODE (Pin 6): Mode Select Input. To select forced con-
tinuous mode, tie to VIN. Grounding this pin selects Burst
Mode operation. Do not leave this pin floating.
REF (Pin 7): External Reference Input. Controls the output
voltage to 3× the applied voltage at REF. Also turns on the
bypass MOSFET when VREF > 1.2V.
VOUT (Pin 8): Output Voltage Feedback Pin. An internal
resistive divider divides the output voltage down by 3 for
comparison to the external reference voltage. The drain of
the P-channel bypass MOSFET is connected to this pin.
Exposed Pad (Pin 9): Connect to GND, Pin 3.
W
FU CTIO AL DIAGRA
MODE
6
REF
7
VOUT
8
RUN
5
SLOPE
COMP
OSC
OSC
0.65V
FREQ
÷2
+
FB
– EA
360k
180k
–
BCMP
1.2V +
P-CHANNEL
VIN
0.85V
– EN SLEEP
+
BURST
SQ
RQ
RS LATCH
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ICOMP
ANTI-
SHOOT-
THRU
IRCMP
2 VIN
5Ω
4 SW
9
3 GND
1 GDR
3403 BD
3403f
7
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