
APPLICATIONS INFORMATION
LTC1404
CLK
CONV
INTERNAL
S/H STATUS
SAMPLE
DOUT
t2
t3
t7
1
2
34
5
6
7
8
9 10 11 12 13 14 15 16 1
2
t4
t5
t6
HOLD
tACQ
SAMPLE
t8
Hi-Z
Hi-Z
REFRDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
REFRDY BIT + 12-BIT DATA WORD
tCONV
tSAMPLE
HOLD
REFRDY
1404 F13
Figure 13. ADC Digital Timing Diagram
CLK
DOUT
VIH
t8
t 10
VOH
VOL
CLK
DOUT
Figure 14. CLK to DOUT Delay
VIH
t9
90%
10%
1404 F14
1404fa
17