LTC1290CCSW(Rev_C) View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1290CCSW Datasheet PDF : 28 Pages
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LTC1290
APPLICATI S I FOR ATIO
larger current limiting resistors. Use 1N4148 diode clamps
from the MUX inputs to VCC and V – if the value of the series
resistor will not allow the maximum clock speeds to be
used or if an unknown source is used to drive the LTC1290
MUX inputs.
How the various power supplies to the LTC1290 are
applied can also lead to overvoltage conditions. For single
supply operation (i.e., unipolar mode), if VCC and REF+ are
not tied together, then VCC should be turned on first, then
REF+. If this sequence cannot be met, connecting a diode
from REF+ to VCC is recommended (see Figure 21).
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V– to ground (Figure 23) will prevent
power supply reversal from occuring when an input source
is applied to the analog MUX before power is applied to the
device. Power supply reversal occurs, for example, if the
input is pulled below V– then VCC will pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC then
V– will be pulled a diode drop above ground. If no inputs
are present on the MUX, the Schottky diodes are not
required if V– is applied first, then VCC.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
20
VCC
LTC1290
1N4148
5V
22µF
REF+ 14
Figure 21
VREF
1290 F21
VCC
5V
1N5817
22µF
LTC1290
DGND
V–
AGND
1N5817
–5V
0.1µF
1290 F22
Figure 22. Power Supply Reversal
TYPICAL APPLICATI S
A “Quick Look” Circuit for the LTC1290
A “Quick Look” Circuit for the LTC1290
Users can get a quick look at the function and timing of the
LTC1290 by using the following simple circuit. REF+ and
22µF LTC1290
5V
f/128
DIN are tied to VCC selecting a 5V input span, CH7 as a
CHO
VCC
single-ended input, unipolar mode, MSB-first format and
16-bit word length. ACLK and SCLK are tied together and
driven by an external clock. CS is driven at 1/128 the clock
rate by the CD4520 and DOUT outputs the data. All other
CH1
ACLK
CLK
VDD
f
CH2
SCLK
EN
RESET
CH3
DIN
CH4
DOUT
CH5
CS
Q1
Q4
Q2 CD4520 Q3
Q3
Q2
0.1µF
pins are tied to a ground plane. The output data from the
CH6
REF+
Q4
Q1
DOUT pin can be viewed on an oscilloscope which is set up VIN
to trigger on the falling edge of CS.
CH7
COM
DGND
REF–
V–
AGND
RESET
EN
VSS
CLK
CLOCK IN
2MHz MAX
1290 TA02
TO
OSCILLOSCOPE
24
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