LTC559X View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC559X Datasheet PDF : 20 Pages
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LTC5567
Applications Information
R3
L1
L2
ICC
VCC
34mA
8
IADJ
11 IF+
VCC
10 IF–
6
VCC
3mA
BIAS
55mA
BIAS
LTC5567
5567 F12
Figure 15. IADJ Interface
in Figure 15, a portion of the reference current can be
shunted to ground, resulting in reduced mixer core cur-
rent. For example, R3 = 1k will shunt away 1mA from Pin
8 and reduce the mixer core current by 33%. The nominal,
open-circuit DC voltage at the IADJ pin is 2.2V. Table 7
lists DC supply current and RF performance at 1950MHz
for various values of R3.
Table 7. Mixer Performance with Reduced Current
(RF = 1950MHz, Low Side LO, IF = 153MHz)
R3 (Ω) ICC (mA) GC (dB)
IIP3
(dBm)
P1dB
(dBm)
Open
89.0
1.9
26.9
10.2
10k
84.6
1.9
25.7
10.2
1k
70.4
1.6
21.4
10.1
330
62.9
1.3
19.3
9.5
100
58.3
1.0
17.9
8.5
NF (dB)
11.8
11.5
10.5
10.3
10.1
Enable Interface
Figure 16 shows a simplified schematic of the enable
interface. To enable the mixer, the EN voltage must be
higher than 2.5V. If the enable function is not required,
the pin should be connected directly to VCC. The volt-
age at the EN pin should never exceed the power supply
voltage (VCC) by more than 0.3V. If this should occur, the
supply current could be sourced through the ESD diode,
potentially damaging the IC.
LTC5567
CLAMP
CMOS
6
VCC
500Ω EN
4 EN
300k
5567 F16
Figure 16. Enable Input Circuit
The EN pin has an internal 300k pull-down resistor.
Therefore, the mixer will be disabled with the enable pin
left floating.
Supply Voltage Ramping
Fast ramping of the supply voltage can cause a current
glitch in the internal ESD clamp circuits connected to the
VCC pin. Depending on the supply inductance, this could
result in a supply voltage transient that exceeds the 4.0V
maximum rating. A supply voltage ramp time greater than
1ms is recommended.
Spurious Output Levels
Mixer spurious output levels versus harmonics of the
RF and LO are tabulated in Table 8. The spur levels were
measured on a standard evaluation board using the test
circuit shown in Figure 1. The spur frequencies can be
calculated using the following equation:
fSPUR = (M • fRF) – (N • fLO)
Table 8. IF Output Spur Levels (dBm)
(RF = 1950MHz, PRF = –2dBm, PIF = 0dBm at 153MHz, Low Side
LO, PLO = 0dBm, VCC = 3.3V, TC = 25°C)
N
0 1 23456789
0
–43 –24 –47 –30 –57 –46 –64 –50 –81
1 –30 0 –56 –57 –59 –37 –69 –47 –78 –58
2 –60 –56 –67 –68 –72 –78 –78 –85 –87 *
M 3 * –81 –89 * * * * * * *
4 * * –73 * * * * * –90 *
5* * * * * * * * * *
6
* ********
7
**
*
*Less than –90dBc
5567f
17
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