EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 95. Input Capture Block Diagram
ICAP1
EDGE DETECT EDGE DETECT
ICIE
ICAP2
CIRCUIT2
CIRCUIT1
IC2R
IC1R
ICF1
16-BIT
16-BIT FREE RUNNING
COUNTER
(Control Register 1) CR1
IEDG1
(Status Register) SR
ICF2
0
0
0
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 96. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
FF01
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
FF02
FF03
FF03
172/429
9