
STM32F101x4, STM32F101x6
Figure 31. SPI timing diagram - master mode(1)
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTU T
tsu(MI)
tw(SCKH)
tw(SCKL)
MS BIN
th(MI)
M SB OUT
tv(MO)
BI T6 IN
B I T1 OUT
th(MO)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Electrical characteristics
tr(SCK)
tf(SCK)
LSB IN
LSB OUT
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Doc ID 15058 Rev 5
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