STM32F101C6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM32F101C6
STMicroelectronics
STM32F101C6 Datasheet PDF : 79 Pages
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Electrical characteristics
STM32F101x4, STM32F101x6
5.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO input low
level voltage
VIL IO FT(1) input low level
voltage
–0.3
–0.3
0.28*(VDD-2 V)+0.8 V V
0.32*(VDD-2V)+0.75 V V
Standard IO input high
level voltage
VIH IO FT(1) input high level VDD > 2 V
voltage
VDD ≤ 2 V
Standard IO Schmitt
trigger voltage
Vhys hysteresis(2)
IO FT Schmitt trigger
voltage hysteresis(2)
0.41*(VDD-2 V)+1.3 V
0.42*(VDD-2 V)+1 V
200
5% VDD(3)
VDD+0.3
V
5.5
V
5.2
mV
mV
VSS ≤ VIN ≤ VDD
Standard I/Os
Ilkg Input leakage current (4)
VIN = 5 V
I/O FT
±1
µA
3
RPU
Weak pull-up equivalent
resistor(5)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
30
40
50
kΩ
CIO I/O pin capacitance
5
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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Doc ID 15058 Rev 5
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