LFECP20E-3TN100I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

LFECP20E-3TN100I

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

sysI/O Single-Ended DC Electrical Characteristics

Input/Output

VIL

Standard Min. (V) Max. (V)

VIH

VOL Max. VOH Min.

Min. (V) Max. (V) (V)

(V)

IOL1

(mA)

IOH1

(mA)

LVCMOS 3.3

-0.3

0.8

2.0

3.6

0.4

VCCIO - 0.4

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

0.2

VCCIO - 0.2

0.1

-0.1

LVTTL

-0.3

0.8

2.0

3.6

0.4

VCCIO - 0.4

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 2.5

-0.3

0.7

1.7

3.6

0.4

VCCIO - 0.4

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 1.8

-0.3 0.35VCCIO 0.65VCCIO

3.6

0.4

VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4

0.2

VCCIO - 0.2

0.1

-0.1

LVCMOS 1.5

-0.3 0.35VCCIO 0.65VCCIO

3.6

0.4

VCCIO - 0.4

8, 4

0.2

VCCIO - 0.2

0.1

-8, -4

-0.1

LVCMOS 1.2

-0.3

0.35VCC

0.65VCC

3.6

0.4

VCCIO - 0.4

6, 2

0.2

VCCIO - 0.2

0.1

-6, -2

-0.1

PCI

-0.3

0.3VCCIO

0.5VCCIO

3.6 0.1VCCIO 0.9VCCIO

1.5

-0.5

SSTL3 class I

-0.3 VREF - 0.2 VREF + 0.2

3.6

0.7

VCCIO - 1.1

8

-8

SSTL3 class II

-0.3 VREF - 0.2 VREF + 0.2

3.6

0.5

VCCIO - 0.9

16

-16

SSTL2 class I

-0.3 VREF - 0.18 VREF + 0.18 3.6

0.54 VCCIO - 0.62

7.6

-7.6

SSTL2 class II

-0.3 VREF - 0.18 VREF + 0.18 3.6

0.35 VCCIO - 0.43

15.2

-15.2

SSTL18 class I

-0.3 VREF - 0.125 VREF + 0.125 3.6

0.4

VCCIO - 0.4

6.7

-6.7

HSTL15 class I

-0.3 VREF - 0.1 VREF + 0.1

3.6

0.4

VCCIO - 0.4

8

-8

HSTL15 class III -0.3 VREF - 0.1 VREF + 0.1 3.6

0.4

VCCIO - 0.4

24

-8

HSTL18 class I

-0.3 VREF - 0.1 VREF + 0.1

3.6

0.4

VCCIO - 0.4

9.6

-9.6

HSTL18 class II

-0.3 VREF - 0.1 VREF + 0.1

3.6

0.4

VCCIO - 0.4

16

-16

HSTL18 class III -0.3 VREF - 0.1 VREF + 0.1 3.6

0.4

VCCIO - 0.4

24

-8

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

3-6

Share Link: