IS25LD256C-JDLE View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

MFG CO.

IS25LD256C-JDLE

256Kbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface

Integrated Silicon Solution 

IS25LD256C

CONNECTION DIAGRAMS

CE#

1

8

SO

2

7

Vcc

HOLD#

WP#

3

GND

4

6

SCK

5

SIO

CE#

SO

WP#

GND

8-Pin SOIC

1

8

2

7

3

6

4

5

8-Pin TSSOP

Vcc

HOLD#

SCK

SI

PIN DESCRIPTIONS

SYMBOL TYPE

DESCRIPTION

CE#

SCK

SIO

SO

GND

Vcc

WP#

HOLD#

INPUT

INPUT

INPUT/OUTPUT

OUTPUT

INPUT

INPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (Sl), and the

serial output pin (SO) will remain in a high impedance state.

Serial Data Clock

Serial Data Input/Output

Serial Data Output

Ground

Device Power Supply

Write Protect: A hardware program/erase protection for all or part of a

memory array. When the WP# pin is low, memory array write-protection depends

on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is

high, the devices are not write-protected.

Hold: Pause serial communication by the master device without resetting

the serial sequence.

Integrated Silicon Solution, Inc.- www.issi.com

2

Rev. A

09/11/2012

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