EP7212-CV View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

EP7212-CV

High-Performance, Low-Power System-on-Chip with LCD Controller and Digital Audio Interface (DAI)

Cirrus Logic 

EP7212

samples deep and the receive FIFO’s are 12 audio

samples deep.

3.13.2.1 DAI Operation

Following reset, the DAI logic is disabled. To en-

able the DAI, the applications program should first

clear the emergency underflow and overflow status

bits, which are set following the reset, by writing a

1 to these register bits (in the DAISR register).

Next, the DAI control register should be pro-

grammed with the desired mode of operation using

a word write. The transmit FIFOs can either be

“primed” by writing up to eight 16-bit values each,

or can be filled by the normal interrupt service rou-

tine which handles the DAI FIFOs. Finally, the

FIFOs for each channel must be enabled via writes

to DAIDR2. At this point, transmission/reception

of data begins on the transmit (SDOUT) and re-

ceive (SDIN) pins. This is synchronously con-

trolled by the 9.216 MHz (6.5 MHz in 13 MHz

mode) internal clock or the externally supplied bit

clock (SCLK), and the serial frame clock (LRCK).

3.13.2.2 DAI Frame Format

Each DAI frame is 128 bits long and it comprises

one audio sample. Of this 128-bit frame, only

32 bits are actually used for digital audio data. The

remaining bits are output as zeros. The LRCK sig-

nal is used as a frame synchronization signal. Each

transition of LRCK delineates the left and right

halves of an audio sample. When LRCK transitions

from high to low the next 16-bits make up the left

7209

SDIN

SCLK

LRCK

SDOUT

MCLK

DAI ADC

SCLK

LRCK

SDATA

MCLK

DAI DAC

SCLK

LRCK

SDATA

MCLK

CLOCK

GEN

Figure 7. DAI Interface

DS474PP1

41

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