JS28F128J3C-110 View Datasheet(PDF) - Intel

Part Name

Description

MFG CO.

JS28F128J3C-110

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

Figure 25. Clear Lock-Bit Flowchart

Start

Write 60H

Write D0H

Read Status Register

0

SR.7 =

1

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

1

SR.3 =

0

1

SR.4,5 =

0

1

SR.5 =

0

Clear Block Lock-Bits

Successful

Voltage Range Error

Command Sequence

Error

Clear Block Lock-Bits

Error

Bus

Operation

Write

Write

Command

Comments

Clear Block

Lock-Bits Setup

Data = 60H

Addr = X

Clear Block or Data = D0H

Lock-Bits Confirm Addr = X

Read

Status Register Data

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

Write FFH after the clear lock-bits operation to place device in read

array mode.

Bus

Operation

Standby

Standby

Standby

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

Check SR.4, 5

Both 1 = Command Sequence

Error

Check SR.5

1 = Clear Block Lock-Bits Error

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register

command.

If an error is detected, clear the status register before attempting retry

or other error recovery.

66

Datasheet

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