DSPIC30F0013CT-30I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

DSPIC30F0013CT-30I/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

4.0 ADDRESS GENERATOR UNITS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

The dsPIC DSC core contains two independent

address generator units: the X AGU and Y AGU. The Y

AGU supports word-sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs sup-

port three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Reversed Addressing

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressing is only applicable to data space addresses.

4.1 Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of

the addressing modes optimized to support the specific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

register instructions employ a working register, W0,

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a register or register pair. The

MOV instruction allows additional flexibility and can

access the entire data space during file register

operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the

addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory or a 5-bit literal. The result

location can be either a W register or an address

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

Note:

Not all instructions support all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode

Description

File Register Direct

The address of the File register is specified explicitly.

Register Direct

The contents of a register are accessed directly.

Register Indirect

The contents of Wn forms the EA.

Register Indirect Post-modified

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

© 2007 Microchip Technology Inc.

DS70138E-page 35

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