August 1986
Revised March 2000
DM74LS03
Quad 2-Input NAND Gates with Open-Collector Outputs
General Description
This device contains four independent gates each of which
performs the logic NAND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where:
N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (IIL) = total maximum input low current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number Package Number
Package Description
DM74LS03M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS03N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y = AB
Inputs
A
B
L
L
L
H
H
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
Output
Y
H
H
H
L
© 2000 Fairchild Semiconductor Corporation DS006344
www.fairchildsemi.com