CS8422-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8422-DNZR Datasheet PDF : 82 Pages
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CS8422
There are a number of conditions that will inhibit the buffer update. If the CS_UPDATE bit in “Receiver Sta-
tus (16h)” is set to ‘0’, the only condition that will inhibit the update is PLL phase unlock. If the CS_UPDATE
bit in “Receiver Status (16h)” is set to ‘1’, a biphase, confidence, parity, or CRC error will also inhibit the
update.
From
AES3
Receiver
Received
Data
Buffer
24 words
D
A
B
8-bits 8-bits
E 5 words
Control
Port
Registers
C Data Serial Output
Figure 34. Channel Status Data Buffer Structure
12.4.2 Accessing the E buffer
The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of
the CS8422, through the control port.
The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is a D to E inhibit bit in the “Receiver Data Control (04h)” register. This may be used whenever
“long” control port interactions are occurring or for debugging purposes.
A flowchart for reading the E buffer is shown in Figure 35. Since a D to E interrupt occurs just after reading,
there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time).
This is usually enough time to access the E data without having to inhibit the next transfer.
D to E interrupt occurs
Optionally set D to E inhibit
Read E data
If set, clear D to E inhibit
Return
Figure 35. Flowchart for Reading the E Buffer
DS692F1
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