CS8422-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8422-DNZR Datasheet PDF : 82 Pages
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CS8422
11.5 GPO Control 1 (05h)
7
6
5
GPO0SEL3 GPO0SEL2 GPO0SEL1
0
0
0
4
GPO0SEL0
0
3
GPO1SEL3
0
2
GPO1SEL2
0
1
GPO1SEL1
0
0
GPO1SEL0
0
GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See Table 7 for available outputs for
GPO[3:0].
11.6 GPO Control 2 (06h)
7
6
5
GPO2SEL3 GPO2SEL2 GPO2SEL1
0
0
0
4
GPO2SEL0
0
3
GPO3SEL3
0
2
GPO3SEL2
0
1
GPO3SEL1
0
0
GPO3SEL0
0
GPOxSEL[3:0] – GPO Source select for GPO2 and GPO3 pins. See Table 7 for available outputs for
GPO[3:0].
Function
GND
VL
EMPH
INT
C
U
RERR
NVERR
RCBL
96KHZ
192KHZ
AUDIO
VLRCK
TX
SRC_UNLOCK
XTI_OUT
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Definition
Fixed low level
Fixed VL level.
State of EMPH bit in the incoming data stream
CS8422 interrupt output
Channel status bit
User data bit
Receiver Error
Non-Validity Receiver Error
Receiver Channel Status Block
Defined in “PLL Status (15h)” on page 60.
Defined in “PLL Status (15h)” on page 60.
Non-audio indicator for decoded input stream
Virtual LRCK, can be used to frame the C and U output data.
Pass through of AES/SPDIF input selected by TXSEL[2:0] in Section 11.3
“Receiver Input Control (03h)” on page 48.
SRC unlock indicator
Buffered XTI-XTO output
Table 7. GPO Pin Configurations
11.7 Serial Audio Input Clock Control (07h)
7
6
5
4
3
SAI_CLK3 SAI_CLK2 SAI_CLK1 SAI_CLK0 SAI_MCLK
0
1
0
0
0
2
Reserved
1
Reserved
0
Reserved
SAI_CLK[3:0] – Selects the serial audio input master clock-to-ILRCK ratio when the serial audio input port
is set to master mode (SIMS = 1 as shown in “Serial Audio Input Data Format (0Bh)” on page 53). Note: if
a serial audio output is sourced directly by the serial audio input port, SAI_CLK[3:0] determine the
MCLK/LRCK ratio for both serial ports if they are set to master mode.
0000 - ILRCK = MCLK/64
50
DS692F1
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