CS8421 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8421 Datasheet PDF : 36 Pages
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DIGITAL INPUT CHARACTERISTICS
CS8421
Input Leakage Current
Input Capacitance
Input Hysteresis
Parameters
Symbol Min Typ Max Units
Iin
-
-
±10
μA
Iin
-
8
-
pF
-
250
-
mV
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA) VOH
Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA)
VOL
High-Level Output Voltage, MCLK_OUT
(IOH=-6 mA) VOH
Low-Level Output Voltage, MCLK_OUT
High-Level Output Voltage, SDOUT
Low-Level Output Voltage, SDOUT
High-Level Input Voltage
Low-Level Input Voltage
(IOL=6 mA)
(IOH=-8 mA)
(IOL=8 mA)
VOL
VOH
VOL
VIH
VIL
Min
0.77xVL
-
0.77xVL
-
0.77xVL
-
0.6xVL
-0.3
Max
-
.6
-
.6
-
.65
VL+0.3
0.8
Units
V
V
V
V
V
V
V
V
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameters
Symbol
RST pin Low Pulse Width
XTI Frequency (Note 7)
XTI Pulse Width High/Low
MCLK_OUT Duty Cycle
Slave Mode
(Note 6)
Crystal
Digital Clock Source
I/OSCLK Frequency
OLRCK High Time
I/OSCLK High Time
I/OSCLK Low Time
I/OLRCK Edge to I/OSCLK Rising
OLRCK Rising Edge to OSCLK Rising Edge (TDM)
I/OSCLK Rising Edge to I/OLRCK Edge
OSCLK Rising Edge to OLRCK Falling Edge (TDM)
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
(Note 8)
tlrckh
tsckh
tsckl
tlcks
tfss
tlckd
tfsh
tdpd
tds
tdh
Min
1
16.384
1.024
14.8
45
-
326
9
9
6
5
5
5
-
3.5
5
Max
-
27.000
27.000
-
55
Units
ms
MHz
MHz
ns
%
24.576
-
-
-
-
-
-
-
18
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS641F4
13
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