CS8420-DSZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8420-DSZR Datasheet PDF : 94 Pages
| |||
CS8420
4. DATA I/O FLOW AND CLOCKING OPTIONS
The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an
associated clocking set-up. Figure 6 shows the data flow switching, along with the control register bits which control
the switches. This drawing only shows the audio data paths for simplicity. Figure 7 shows the internal clock routing
and the associated control register bits. The clock routing constraints determine which data routing options are ac-
tually usable.
ILRCK
ISCLK
SDIN
RXN
RXP
Serial
Audio
Input
AES3
Receiver
SRCD
Sample
Rate
Converter
SPD1-0
Serial
Audio
Output
AESBP TXOFF
AES3
Encoder
TXD1-0
OLRCK
OSCLK
SDOUT
TXP
TXN
Figure 6. Software Mode Audio Data Flow Switching Options
SDIN
ISCLK
ILRCK
RXP
SERIAL
AUDIO
INPUT
RXD0
0
MUX
1
PLL
SIMS
SAMPLE
RATE
CONVERTER
RMCKF
÷
MUX
1
0
INC
CHANNEL
STATUS
MEMORY
SERIAL
AUDIO
OUTPUT
AES3
TRANSMIT
SDOUT
OSCLK
OLRCK
TXN
TXP
1
0
MUX
SWCLK
UNLOCK
USER
BIT
MEMORY
RMCK
0
MUX
1
RXD1
MUX
1
0
OUTC
÷
CLK[1:0]
OMCK
*Note: When SWCLK mode is enabled, signal input on OMCK is only output through RMCK and not
routed back through the RXD1 multiplexer; RMCK is not bi-directional in this mode.
Figure 7. CS8420 Clock Routing
14
DS245F4
Share Link: 