CS8416-CS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8416-CS

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

9. PIN DESCRIPTION - SOFTWARE MODE

RXP3 1

RXP2 2

RXP1 3

RXP0 4

RXN 5

VA+ 6

AGND 7

FILT 8

RST 9

RXP4 10

RXP5 11

RXP6 12

RXP7 13

AD0/CS 14

28 OLRCK

27 OSCLK

26 SDOUT

25 OMCK

24 RMCK

23 VD+

22 DGND

21 VL+

20 GPO0

19 GPO1

18 AD2/GPO2

17 SDA/CDOUT

16 SCL/CCLK

15 AD1/CDIN

CS8416

RXP[7:0]

RXN

VA+

VD+

VL+

AGND

DGND

FILT

13 Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or

12 S/PDIF digital data. These inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is

11 accessed using the Control 4 register. Please note that any unused inputs can be left floating or tied to

10 ground. See Appendix A for recommended input circuits.

1

2

3

4

5 AES/SPDIF input - Used along with RXP[X] to form an AES3 differential input. In single-ended

operation this should be capacitively coupled to ground.

6 Positive Analog Power - Positive supply for the analog section. Nominally +3.3 V. This supply should

be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered

clock

23 Positive Digital Power – Nominally 3.3 V

21 Positive – Interface Power – 3.3 V to 5.0 V: this supply sets the CS8416 I/O levels, including RXPx &

RXN

6 Analog Ground - Ground for the analog circuitry in the chip. AGND and DGND should be con nected

to a common ground area under the chip.

22 Digital & I/O Ground

8 PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND

DS578PP2

35

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