CS8416-DNZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8416-DNZR

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX source

Default =’001’

000 – RXP0

001 – RXP1, etc

CS8416

14.7 Serial Audio Data Format (05h)

7

6

5

4

SOMS

SOSF

SORES1

SORES0

3

SOJUST

2

SODEL

1

SOSPOL

0

SOLRPOL

SOMS - Master/Slave Mode Selector

Default = ‘0’

0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.

1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.

SOSF - OSCLK frequency (for master mode)

Default = ‘0’

0 - OSCLK output frequency is 64*Fs.

1 - OSCLK output frequency is 128*Fs.

SORES[1:0] - Resolution of the output data on SDOUT

Default = ‘00’

00 - 24-bit resolution.

01 - 20-bit resolution.

10 - 16-bit resolution.

11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time slot

occupied by the Z bit is used to indicate the location of the block start. This setting forces the SOJUST bit

to be “0”. When using this setting, the de-emphasis filter must be off.

SOJUST - Justification of SDOUT data relative to OLRCK

Default = ‘0’

0 - Left-Justified.

1 - Right-Justified (master mode only and SORES ≠11).

SODEL - Delay of SDOUT data relative to OLRCK, for Left-Justified data formats

(This control is only valid in Left-Justified Mode)

Default = ‘0’

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge.

1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge.

SOSPOL - OSCLK clock polarity

Default = ‘0’

0 - SDOUT is sampled on rising edges of OSCLK.

1 - SDOUT is sampled on falling edges of OSCLK.

40

DS578F3

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