CS8415A-CSR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8415A-CSR

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

15.3 Component Value Selection

When transitioning from one revision of the part another, component values may need to be changed. While

it is mandatory for customers to change the external PLL component values when transitioning from revision

A to revision A1 or from revision A to revision A2, customers do not need to change external PLL component

values when transitioning from revision A1 to revision A2, unless the part is used in an application that is

required to pass the AES3 or IEC60958-4 specification for receiver jitter tolerance (see Table 6).

15.3.1 Identifying the Part Revision

The first line of the part marking on the package indicates the part number and package type (CS8415A-

xx). Table 4 shows a list of part revisions and their corresponding second line part marking, which indi-

cates what revision the part is.

Pre-October 2002

Revision SOIC & TSSOP (10-Digit)

A

Zxxxxxxxxx

A1

Rxxxxxxxxx

A2

N/A

New SOIC

(12-Digit)

ZFBAAXxxxxxx

RFBAA1xxxxxx

RFBAA2xxxxxx

Table 4. Second Line Part Marking

New TSSOP

(10-Digit)

NAAXxxxxxx

NAA1xxxxxx

NAA2xxxxxx

15.3.2 External Components

Shown in Table 5 and Table 6 are the external PLL component values for each revision. Values listed for

the 32 to 96 kHz Fs range will have the highest corner frequency jitter attenuation curve, take the shortest

time to lock, and offer the best output jitter performance.

Revision

A

A1

A2

RFILT (kΩ)

0.909

0.4

0.4

CFILT (µF)

1.8

0.47

0.47

CRIP (nF)

33

47

47

Table 5. Fs = 8 to 96 kHz

PLL Lock Time (ms)

56

60

60

Revision

A*

A1*

A2

A2*

RFILT (kΩ)

3.0

1.2

1.2

1.6

CFILT (µF)

0.047

0.1

0.1

0.33

CRIP (nF)

2.2

4.7

4.7

4.7

PLL Lock Time (ms)

35

35

35

35

Table 6. Fs = 32 to 96 kHz

* Parts used in applications that are required to pass the AES3 or IEC60958-4 specifica-

tion for receiver jitter tolerance should use these component values. Please note that the

AES3 and IEC60958 specifications do not have allowances for locking to sample rates

less than 32 kHz. Also note that many factors can affect jitter performance in a system.

Please follow the circuit and layout recommendations outlined previously

DS470F4

43

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