CS8412-CS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8412-CS

Digital Audio Interface Receiver

Cirrus Logic 

CS8411 CS8412

each sample and FSYNC has four formats. The

first two output formats of FSYNC (shown in Fig-

ure 10) delineate each word and the identification

of the particular channel must be kept track of ex-

ternally. This may be done using the rising edge of

FLAG2 to indicate the next data word is left chan-

nel data. The last two output formats of FSYNC

also delineate each channel with the polarity of

FSYNC indicating the particular channel. The last

format has FSYNC change one SCK cycle before

the frame containing the data and may be used to

generate an I2S compatible interface.

When SCK is programmed as an input, 32 SCK cy-

cles per sample must be provided. (There are two

formats in the Special Modes section where SCK

can have 16 or 24 clocks per sample.) The four

modes where FSYNC is an input are similar to the

FSYNC output modes. The first two require a tran-

sition of FSYNC to start the sample frame, whereas

the last two are identical to the corresponding

FSYNC output modes. If the circuit generating

SCK and FSYNC is not locked to the master clock

of the CS8411, the serial port will eventually be re-

read or a sample will be missed. When this occurs,

the SLIP bit in SR1 will be set.

SDATA can take on five formats in the normal se-

rial port modes. The first format (see Figure 10),

MSB First, has the MSB aligned with the start of a

sample frame. Twenty-four audio bits are output

including the auxiliary bits. This mode is compati-

ble with many DSPs. If the auxiliary bits are used

for something other than audio data, they must be

masked off. The second format, MSB Last, outputs

data LSB first with the MSB aligned to the end of

the sample frame. This format is conducive to seri-

al arithmetic. Both of the above formats output all

audio bits from the received data. The last three for-

mats are LSB Last formats that output the most sig-

nificant 16, 18, and 20 bits respectively, with the

LSB aligned to the end of the sample frame. These

formats are used by many interpolation filters.

Special Modes

Five special modes are included for unique applica-

tions. In these modes, the master bit, MSTR, must

be defined as shown in Figure 10. In the first mode,

Asynchronous SCK, FSYNC (which is an output in

this mode) is aligned to the incoming SCK. This

mode is useful when the SCK is locked to an exter-

nal event and cannot be derived from MCK. Since

SCK is asynchronous, the number of SCK cycles

per sample frame will vary. The data output will be

MSB first, 24 bits, and aligned to the beginning of

a sample frame. The second and third special

modes are unique in that they contain 24 and 16

SCK cycles respectively per sample frame, where-

as all normal modes contain 32 SCK cycles. In

these two modes, the data is MSB first and fills the

entire frame. The fourth special mode outputs NRZ

data including the V, U, C, and P bits and the pre-

amble replaced with zeros. SCK is an output with

32 SCK cycles per sample frame. The fifth mode

outputs the biphase data recovered from the trans-

mission line with 64 SCK cycles output per sample

frame, with data changing on the rising edge.

Normally, data recovered by the CS8411 is delayed

by two frames in propagating through the part, but

in the fourth and fifth special modes, the data is de-

layed only a few bit periods before being output.

However, error codes, and the C, U and V bits fol-

low their normal pathways with a two frame delay

(so that the error code would be output with the of-

fending data in the other modes). As a result, in

special modes four and five, the error codes are

nearly two frames behind the data output on SDA-

TA.

Buffer Memory

In all buffer modes, the status, mask, and control

registers are located at addresses 0-3, and the user

data is buffered at locations 4 through 7. The paral-

lel port can access any location in the user data

buffer at any time; however, care should be taken

not to read a location when that location is being

14

DS61F1

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