CS8406-DSZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8406-DSZR Datasheet PDF : 42 Pages
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CS8406
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached device through
the control registers. The following parameters are adjustable:
• Master or slave
• Serial clock frequency
• Audio data resolution
• Left or right justification of the data relative to left/right clock
• Optional one-bit cell delay of the first data bit
• Polarity of the bit clock
• Polarity of the left/right clock (by setting the appropriate control bits, many formats are possible.)
Figure 7 shows a selection of common input formats with the corresponding control bit settings.
In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master
clock.
In Slave Mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock
should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks
are present in each phase to clock all the data bits.
ILRCK
Left
ISCLK
Justified
(In)
SDIN
ILRCK
I2S
(In)
ISCLK
SDIN
Left
MSB
Left
MSB
Right
LSB
MSB
Right
LSB
MSB
LSB
MSB
LSB
MSB
ILRCK
Right ISCLK
Justified
(In)
SDIN
LSB
Left
MSB
LSB
Right
MSB
LSB
Left Justified
I²S
Right Justified
SIMS*
X
X
X
SISF*
X
X
X
SIRES[1:0]*
00+
00+
XX
SIJUST*
0
0
1
SIDEL*
0
1
0
SISPOL*
0
0
0
X = don’t care to match format, but does need to be set to the desired setting
+ I²S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 7. Serial Audio Input Example Formats
SILRPOL*
0
1
0
12
DS580F5
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