CS7666 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7666 Datasheet PDF : 42 Pages
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CS7666
SDASEC - Secondary I2C Data Bus, PIN 47.
Secondary I2C data bus with limited bus mastering capabilities. Used with SCLSEC to read and
write I2C devices located on the secondary bus. Various devices can be isolated by the CS7666
from the primary I2C bus. The CS7666 will start reading I2C EPROM devices at addresses A0h
after RESET. It will download the EPROM contents into the specified registers inside the
secondary bus devices as well as any CS7666 registers specified in the EPROM entries.
Devices are typically connected to either the primary or the secondary I2C bus. However, the
two busses may be connected together when system design requires the use of EPROM
initialization while at the same allowing direct access to all the camera devices from the
external I2C controller.
SCLSEC - Secondary I2C Clock, PIN 48.
Secondary I2C clock with limited bus mastering capabilities. Used with SDASEC to read and
write I2C devices located on the secondary bus. Various devices can be isolated by the CS7666
from the primary I2C bus. The CS7666 will start reading I2C EPROM devices at addresses A0h
after RESET, and download the EPROM contents into the specified secondary bus registers, as
well as any CS7666 registers specified in the EPROM entries. Devices are typically connected
to either the primary or the secondary I2C bus. However, the two busses may be connected
together when system design requires the use of EPROM initialization while at the same time
allowing direct access to all the camera devices from the external I2C controller.
4BYTEMODE - Four-byte Mode I2C Operation Enable, PIN 1.
Places CS7666 in the Four-byte mode for I2C transactions on the primary I2C bus. Active high.
Digital Video Outputs and Clocking
DOA[9:0] - "A" Channel Digital Output Bits.
CMOS level 10-bit digital video output channel "A." Either YCrCb interleaved digital video
output data, or Y component digital video data is available at this port according to the state of
bit 5 in register 06h. DOA0(LSB) is the least significant bit of channel "A"; DOA9(MSB) is
the most significant bit of channel "A."
DOB[9:0] - "B" Channel Digital Output Bits.
CMOS level 10-bit digital video output channel "B." Either logic "0" in interleaved digital
video output data mode, or CrCb component digital video data is available at this port
according to the state of bit 5 in register 06h. DOB0(LSB) is the least significant bit of channel
"B;" DOB9(MSB) is the most significant bit of channel "B."
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DS302PP1
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