CS7620-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
4.26 Timing Control - Extra Lines of Exposure in Low Resolution Mode (LSBs)
Default = 00h; Read/Write (address 24h)
Bit Number
Bit Name
Default
7
n_extra7
0
6
n_extra6
0
5
n_extra5
0
4
n_extra4
0
3
n_extra3
0
2
n_extra2
0
1
n_extra1
0
0
n_extra0
0
Bit
Mnemonic
Function
7
n_extra7
Extra Lines: This allows for increased exposure time while in low resolution
6
n_extra6
mode.
5
n_extra5
In low resolution mode, the CS7620 continuously outputs data on a frame by
4
n_extra4
frame basis; so it can drive a LCD panel in a video mode. In this mode the
3
n_extra3
CS7620 ignores the expose signal. The default expose time is equivalent to
262 line times (see registers 25h and 26h, n_int).
2
n_extra2
1
n_extra1
N_extra provides a way to increase the exposure time beyond the one which
is set by register n_int (25h and 26h). The value of n_extra corresponds to the
0
n_extra0
number of line times.
4.27 Timing Control - Vsync Mode, Lines of Exposure in Low Resolution Mode (MSBs)
Default = 01h; Read/Write (address 25h)
Bit Number
Bit Name
Default
7
6
Reserved
-
-
5
vsync_md
0
4
3
2
1
lowres_sen3 lowres_sen2 lowres_sen1 lowres_sen0
0
0
0
0
0
n_int8
1
Bit Mnemonic
7:6
-
5 vsync_md
Function
Reserved
Vertical Sync: Vsync_md, will switch the RD_OUT pin to output a vertical sync signal on this
pin when the vsync_md register is set to 1. The default is 0 which outputs the RD_OUT signal
(see Figures 21 and 22).
44
DS301PP2
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