CS7615 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS7615

CCD Imager Analog Processor

Cirrus Logic 

CS7615

Timing Control-Horizontal Blank Pd Register (40h)

7

HBPD7

r/w

6

HBPD6

r/w

5

HBPD5

r/w

4

HBPD4

r/w

3

HBPD3

r/w

2

HBPD2

r/w

1

HBPD1

r/w

0

HBPD0

r/w

HBPD

Number of pixel clocks in the horizontal blank period. Default is 70h.

Timing Control- Line Length Register (41h-42h)

41h:

7

HLEN9

r/w

6

HLEN8

r/w

5

HLEN7

r/w

4

HLEN6

r/w

3

HLEN5

r/w

2

HLEN4

r/w

1

HLEN3

r/w

0

HLEN2

r/w

42h:

7

6

5

4

3

2

1

0

res

res

res

res

res

res

HLEN1

HLEN0

r

r

r

r

r

r

r/w

r/w

HLEN

Total number of pixels in line length. Default is 270h.

Timing Control- HSYNC Registers (43h-44h)

43h:

7

HSYNR7

r/w

6

HSYNR6

r/w

5

HSYNR5

r/w

4

HSYNR4

r/w

3

HSYNR3

r/w

2

HSYNR2

r/w

1

HSYNR1

r/w

0

HSYNR0

r/w

44h:

7

HSYNF7

r/w

6

HSYNF6

r/w

5

HSYNF5

r/w

4

HSYNF4

r/w

3

HSYNF3

r/w

2

HSYNF2

r/w

1

HSYNF1

r/w

0

HSYNF0

r/w

HSYNR

Number of pixels from HREF to leading edge of HSYNC. Default is 14h.

HSYNF

Number of pixels from HREF to trailing edge of HSYNC. Default is 44h.

Timing Control - Black Clamp Register (45h)

7

6

5

4

3

2

1

0

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

r/w

r/w

r/w

r/w

r/w

r/w

r/w

r/w

BC

Number of pixels from HREF to leading edge of black clamp. Default is 08h. Black clamp falls

on leading edge of HENB.

22

DS231PP6

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