13. APPLICATIONS
DS261PP5
CS61584A
2
2
2
2
3
3
2
REFCLK 1XCLK MODE RESET PD[1:2] CLKE ATTEN[0:1] RLOOP[1:2] LLOOP TAOS[1:2] CON[0:2]1 CON[0:2]2 LOS[1:2]
Clock Generator
TCLK1
Hardware Control
T1 1:N
TTIP1 0.47µ FC1
transmit
Framer
TPOS1
TNEG1
RCLK1
Channel 1
TRING1
R1
T2 1:N
RTIP1 0.47µ F
RPOS1
receive
RNEG1
Framer
TCLK2
TPOS2
TNEG2
RCLK2
Channel 2
RRING1
R2
T3 1:N
TTIP2 0.47µ FC2
transmit
TRING2
R3
T4 1:N
RTIP2
0.47µ F
RPOS2
receive
RNEG2
Power Supply
RRING2
R4
AV+ AGND BGREF TGND2 TV+2 TV+1 TGND1 RGND2 RV+2 RV+1 RGND1 DV+ DGND1:3
0.1 µ F
VCC
+
1 µF
R3
4.99kΩ 0.1 µ F
0.1 µ F
+
22 µ F
0.1 µ F
0.1 µ F
3
0.01 µ F
Figure 27. Hardware Mode Configuration
Device Suffix
-IL3 and -IQ3 (3.3 Volts)
-IL5 and -IQ5 (5.0 Volts)
Data Rate
(MHz)
1.544
2.048
1.544
2.048
REFCLK Frequency (MHz)
1XCLK = 1 1XCLK = 0
1.544
12.352
2.048
16.384
Transformer
Turns Ratio
1:2
1.544
2.048
12.352
16.384
1:1.15
Table 13. CS61584A External Components
Cable R1-R4 C1-C2
(Ω) (Ω) (pF)
100 12.4 560
75 9.31 2200
120 15.0 560
100 38.3 220
75 28.7 470
120 45.3 220
13.1 Line Interface
Figures 27-29 illustrate typical connection diagram
for T1 and E1 line interface circuits in Hardware,
Host serial port, and Host parallel port modes. Ta-
ble 13 lists the external components that are re-
quired in T1 and E1 applications for both the 5.0
and 3.3 Volt devices.
In the transmit line interface circuitry, capacitors
C1 and C2 provide transmitter return loss. The
0.47 µF capacitor in series with the transformer pri-
mary prevents output stage imbalances from pro-
ducing a DC current through the transformer that
might saturate the transformer and result in an out-
put level offset.
In the receive line interface circuitry, resistors R1-
R4 provide receive impedance matching and re-
ceiver return loss. The 0.47 µF capacitor to ground
provides the necessary differential input voltage
reference for the receiver.
48
DDS2S6216P1PF15