CS61584A-IQ3 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS61584A-IQ3

Dual T1/E1 Line Interface

Cirrus Logic 

DS261PP5

CS61584A

9.2 Serial Port Operation

Serial port operation in Host mode is selected when

the MODE pin is set high and the P/S pin is set low.

In this mode, the CS61584A register set is accessed

by setting the chip select (CS) pin low and commu-

nicating over the SDI, SDO, and SCLK pins. Tim-

ing over the serial port is independent of the

transmit and receive system timing. Figure 21 illus-

trates the format of serial port data transfers.

A read or write is initiated by writing an ad-

dress/command byte (ACB) to SDI. During a read

cycle, the register data addressed by the ACB is

output on SDO on the next eight SCLK clock cy-

cles. During a write cycle, the data byte immediate-

ly follows the ACB. A second address byte is

required when reading or writing the Arbitrary

Waveform registers (see below).

Data is written to and read from the serial port in

LSB first format. When writing to the port, SDI in-

put data is sampled by the device on the rising edge

of SCLK. The polarity of the data output on SDO is

controlled by the SPOL pin. When the SPOL pin is

low, data on SDO is valid on the rising edge of

SCLK. When the SPOL pin is high, data on SDO is

valid on the falling edge of SCLK. The SDO pin is

high impedance when not transmitting data. If the

host processor has a bi-directional I/O port, SDI

and SDO may be tied together.

As illustrated in Figure 22, the ACB consists of a

R/W bit, address field, and two reserved bits. The

R/W bit specifies if the current register access is a

read (R/W = 1) or a write (R/W = 0) operation. The

address field specifies the register address from

0x10 to 0x19. The reserved bit must be cleared for

normal operation of serial mode.

During register addressing, the first eight registers

are addressed as 0x10 to 0x17 in the address field

of the ACB. Because Arbitrary Waveform registers

0x18 and 0x19 access multiple bytes of RAM,

reading or writing these registers requires an Ad-

dress Command Byte followed by a RAM address

byte for each data transfer. The ACB specifies ei-

ther 0x18 or 0x19 in the address field to access the

channel 1 or channel 2 Arbitrary Waveform regis-

ter set. The RAM address is an 8-bit, unsigned bi-

nary number in the range of 0x00 to 0x29 to

identify one of 42 RAM locations. The data byte

containing the 7-bit, 2’s complement number spec-

ifying the phase amplitude completes the 24 SCLK

write cycle.

CS

SCLK

SDI

SDO

R/W 0 0 0 0 1 0

Address/Command Byte(s)

Data Input

0 D0 D1 D2 D3 D4 D5 D6 D7

Data Output

D0 D1 D2 D3 D4 D5 D6 D7

Figure 21. Serial Read/Write Format (SPOL = 0)

B7 (MSB)

Reserved

0

B6

Reserved

0

30

B5

ADR4

MSB

B4

ADR3

B3

ADR2

Address Field

B2

ADR1

Figure 22. Address Command byte

B1

ADR0

LSB

B0

R/W

0 = Write

1 = Read

DDS2S6216P1PF15

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