CS61581-IP View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS61581-IP

T1/E1 Universal Line Interface

Cirrus Logic 

CS61581

6.1 Power Supplies

TV+ - Power Supply, Transmit Driver, Pin 15.

Power supply for the transmit driver; typically +5 Volts.

TGND - Ground Transmit Driver, Pin 14.

Power supply ground for the transmit driver; typically 0 Volts.

RV+ - Power Supply, Pin 21.

Power supply for all subcircuits except the transmit driver; typically +5 Volts.

RGND - Ground, Pin 22.

Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.

6.2 Oscillator

XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.

A 6.176 MHz (or 8.192 MHz) crystal can be connected across these pins. This oscillator provides the

reference frequency for the LIU if MCLK is not provided. The load capacitance presented to the crystal

by these pins should be approximately 19 pF (IC and package, when soldered into a circuit board). The

jitter attenuator may be disabled by tying XTALIN to RV+ through a 1 kΩ resistor, and floating

XTALOUT. When XTALIN has no clock input, a clock must be supplied to the MCLK pin. Alternatively an

external 6.176 MHz (8.192 MHz) clock can be driven into XTALIN, and the jitter attenuator circuit will

operate.

If MCLK is provided, and XTALIN is tied low or floated, the jitter attenuator will be enabled.

6.3 Control

MCLK - Master Clock Input, Pin 1.

Either MCLK or the crystal oscillator provide the master frequency reference for the CS61581. If both

MCLK and the crystal oscillator are present, the oscillator is ignored. MCLK should be 1.544 MHz for T1

and 2.048 MHz) for E1. In a Loss of Signal state, RCLK will be derived from MCLK, through the jitter

attenuator, if active. If MCLK is not provided, the jitter attenuator will hold the RCLK frequency in a Loss

of Signal state. MCLK should be grounded if it is not used.

MODE - Mode Select Input, Pin 5.

Setting the MODE pin high puts the CS61581 into Host Mode where the device is controlled by a

microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode

control where various control and status are provided on dedicated pins. The MODE pin is internally

pulled down placing the part in Hardware Mode when this pin is left floating. Tying the MODE pin to

RCLK places the chip in Hardware Mode and enables the B8ZS encoder/decoder (provided that

unipolar mode has been enabled; see the description for TNEG/UBS pin).

TAOS - Transmit All Ones Select Input, Pin 28 (Hardware Mode).

Setting TAOS to logic 1 causes continuous ones to be transmitted at the TCLK frequency. When TAOS

is high, TPOS and TNEG (TDATA) are not output at the TTIP/TRING pins. TAOS is overridden by

Remote Loopback. Setting TAOS, LLOOP, and RLOOP high simultaneously enables Network Loopback

detection.

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DS211PP8

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