CS61581-IP View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS61581-IP Datasheet PDF : 38 Pages
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CS61581
2.21 Interrupts
An interrupt will occur (INT pulls low) in response
to a change in the LOS, AIS or NLOOP bits. The
interrupt is cleared when the host processor writes
a “1” to the respective bit in the control register.
Writing a “1” to LOS or NLOOP over the serial in-
terface has three effects:
1) The current interrupt on the serial interface will
be cleared. (Note that simply reading the regis-
ter bits will not clear the interrupt).
2) Output data bits 5, 6 and 7 will be reset as ap-
propriate.
3) Interrupts for the corresponding LOS and
NLOOP will be prevented from occurring.
Writing a “0” to either LOS or NLOOP enables the
corresponding interrupt for LOS and NLOOP.
Reading the registers returns their current status or
setting. Register 0x10 outputs the status NLOOP
and LOS and has bits 5, 6, and 7 encoded as shown
in Tables 4 and 5.
3. QRSS TEST MODE
In Host Mode, the CS61581 has the capability to
generate and detect a QRSS (220-1 with 14 zeros
_PATH bit (CR3.7) determines whether the pattern
is transmitted on TTIP/TRING or RPOS/RNEG.
Errors can be inserted and counted in the pattern.
The QRSS test mode is controlled through Control
Register 3, address 0x14. Setting QGEN to 1
(CR3.1 = 1) initiates the pattern output. The QRSS
pattern detector is enabled by writing a 1 to QDET
(CR3.4 = 1).
When the detector synchronizes to an input pattern,
QSYNC is set to 1. Errors detected in the received
QRSS pattern are counted and stored in the Data
Pattern Error Count, DPEC, register at address
0x15. An error can be inserted in the output data
pattern by setting INS_QERR bit to 1 then 0. The
number of errors accumulated by the pattern detec-
tor are stored in the DPEC register. The DPEC reg-
ister will accumulate to all ones, 255 errors, and
stay at that level until reset. The DPEC register is
reset to zero by setting the RST_QERR bit to 1
(CR3.3 = 1)
Bits
765
Long Haul Mode Status
0 0 0 Reset has occurred, or no program input
0 0 1 RLOOP active
0 1 0 LLOOP active
0 1 1 LOS has changed state since last Clear
LOS occurred
1 0 0 TAOS active
1 0 1 NLOOP has changed state since last
Clear NLOOP occurred
1 1 0 TAOS and LLOOP active
1 1 1 LOS and NLOOP have both changed
state since last Clear NLOOP and Clear
LOS
Table 4. Register 0x10 Decoding
Bits
765
Short Haul Mode Status
0 0 0 Reset has occurred, or no program input
0 0 1 RLOOP active
0 1 0 LLOOP active
0 1 1 LOS has changed state since last Clear
LOS occurred
1 0 0 TAOS active
1 0 1 Not used
1 1 0 TAOS and LLOOP active
1 1 1 Not Used
Table 5. Register 0x10 Decoding
DS211PP8
23
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