CS5560(2008) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5560
(Rev.:2008)

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

3/25/08

CS5560

At the same time the converter is performing a conversion on a channel from one bank of multiplexers,

the second multiplexer bank is used to select the channel for the next conversion. This configuration al-

lows the buffer amplifier for the second multiplexer bank to fully settle while a conversion is being per-

formed on the channel from the first multiplexer bank. The multiplexer on the output of the buffer amplifier

and the CONV signal can be changed at the same time in this configuration. This multiplexing architec-

ture allows for maximum multiplexing throughput from the A/D converter. The following figure depicts the

recommended analog input amplifier circuit.

CH1

B1+

B2+

SW2

B1-

B2-

CH2

CH3

C1+

C2+

SW3

C1-

C2-

CH4

49.9

47pF

4.99k

4700pF

C0G

49.9

47pF

4.99k

4700pF

C0G

49.9

47pF

4.99k

4700pF

C0G

49.9

47pF

4.99k

4700pF

C0G

CS556x

A1+

AIN+

A2+

SW1

A1-

AIN-

A2-

CONV

SW1

SW2

SW3

Select A1

Select B1

Select C1

Select A2

Select B2

Select A1

Select C2

Select A2

Select B1

Select A1

Select C1

Convert on CH1 Convert on CH3 Convert on CH2 Convert on CH4 Convert on CH1

Figure 23. More Complex Multiplexing Scheme

3.13 Synchronizing Multiple Converters

Many measurement systems have multiple converters that need to operate synchronously. The convert-

ers should all be driven from the same master clock. In this configuration, the converters will convert syn-

chronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge

of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters

if RST is released on a falling edge of MCLK.

DS713PP1

27

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