CS5540-AS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5540-AS Datasheet PDF : 22 Pages
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CS5540
SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = +3.0 V ±5% VA- = 0 V, VD+ = 3.0 V ±5%,
DGND = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF)
Parameter
Symbol Min Typ Max Units
Master Clock Frequency:
Master Clock Duty Cycle
Rise Times
Fall Times
Start-up
Oscillator Start-up Time
Power-on Reset Period
External Clock MCLK
Internal Oscillator (Note 18)
(Note 19) trise
Any Digital Input Except SCLK
SCLK
SDO Output
(Note 19) trise
Any Digital Input Except SCLK
SCLK
SDO Output
XTAL = 32.768 kHz (Note 20) tost
tpor
Serial Port Timing
Serial Clock Frequency
Serial Clock
CS Enabled to SCLK Rising
SCLK falling prior to Chip Select Disabled
SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
Pulse Width High
Pulse Width Low
SCLK
t1
t2
t3
t4
t5
t6
t7
5
-
40 kHz
- 32.768 -
40
-
60
%
-
-
1.0 µs
-
-
100 µs
-
50
-
ns
-
-
1.0 µs
-
-
100 µs
-
50
-
ns
-
500
-
ms
-
490
- MCLK
cycles
0
-
250
-
250
-
50
-
100
-
2 MHz
-
ns
-
ns
-
ns
-
ns
-
-
150 ns
-
-
150 ns
-
-
150 ns
Notes: 18. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for
increased throughput.
19. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
20. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
8
DS503PP1
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