CS5540-AS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5540-AS

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Cirrus Logic 

CS5540

by CHS, the channel being converted can be

switched at any time. The conversion in-process

when CHS is switched will be aborted and a new

conversion will begin on the selected channel. The

indicator bits in the SDO output will indicate which

channel was converted.

2.6.1 Switching Channels

7358 clock cycles after CHS is toggled, SDO will

fall (indicating new data present). All subsequent

data will be presented to the serial port every 4884

clock cycles, as portrayed in Figure 8.

2.7 Serial Port and Data Conversions

When power is applied to the CS5540, it is reset by

the power-on reset circuit. Then the converter en-

ters the data mode where the ADC continuously

converts the analog input channel selected by the

channel select pin (CHS). After a conversion is

complete, the SDO pin falls to logic 0 to indicate an

end of conversion and the next 32 serial clock puls-

es shift data out of the serial port. Figure 8 illus-

trates the sequence necessary to read output data

from the data conversion register.

The CS5540 operates in a self-calibration mode

which allows the converter to calibrate continuous-

ly between each conversion (if a user requires sys-

tem calibration, this can be accommodated in the

system microcontroller). The sections that follow

detail the conversion mode and also explain how to

decode the conversion word into the respective flag

and data bits.

Note:

The CS5540 offers self calibration, in which

the ADC calibrates out offset and gain errors

due to the ADC itself. Calibration in the

CS5540 is used to set the zero and gain slope

of the ADC’s transfer function. For the

self-calibration of offset, the converter

internally ties the inputs of the modulator

together and routes them to the VREF- pin as

shown in Figure 9. VREF- must be tied to a

fixed voltage between VA+ and VA-. For

self-calibration of gain, the differential inputs

of the modulator are connected to VREF+

and VREF- as shown in Figure10. Further

note that each calibration step (offset or gain)

is transparent to the user and is included in

the specified 6.7 SPS output rate.

AIN+

+

AIN-

-

VREF-

Figure 9. Self Calibration of Offset

SCLK

CHS

SDI set low while

reading status & data

td *

to *

SDO

0

1 1 1 1 CH OD OF MSB

LSB

* td = 7358 clock cycles

to = 4884 clock cycles

8 SCLKs to read status

Data Time

24 SCLKs

Figure 8. Command and Data Word Timing

DS503PP1

13

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