CS5530 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5530 Datasheet PDF : 36 Pages
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CS5530
3. PIN DESCRIPTIONS
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
AMPLIFIER CAPACITOR CONNECT
AMPLIFIER CAPACITOR CONNECT
POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER
LOGIC OUTPUT (ANALOG)
LOGIC OUTPUT (ANALOG)
MASTER CLOCK
MASTER CLOCK
AIN1+ 1
20
AIN1-
C1
2
19
CS5530
3
18
C2 4
17
VA+ 5
16
VA- 6
15
A0 7
14
A1 8
13
OSC2 9
12
OSC1 10
11
NC
NC
VREF+
VREF-
DGND
VD+
CS
SDI
SDO
SCLK
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIGITAL GROUND
POSITIVE DIGITAL POWER
CHIP SELECT
SERIAL DATA INPUT
SERIAL DATA OUT
SERIAL CLOCK INPUT
Clock Generator
OSC1; OSC2 – Master Clock
An inverting amplifier inside the chip is connected between these pins and can be used with a
crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible)
clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock
for the device.
Control Pins and Serial Data I/O
CS – Chip Select
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
SDI – Serial Data Input
SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.
SDO – Serial Data Output
SDO is the serial data output. It will output a high impedance state if CS = 1.
SCLK – Serial Clock Input
A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins
respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin
will recognize clocks only when CS is low.
A0 – Logic Output (Analog), A1 – Logic Output (Analog)
The logic states of A1-A0 mimic the A1-A0 bits in the Configuration Register. Logic
Output 0 = VA-, and Logic Output 1 = VA+.
32
DS742F3
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